(1) Field Of The Invention
The present invention relates to a method of making advanced multilevel interconnections on integrated circuits, and more particularly relates to a method for an improved copper damascene process that uses a low-k dielectric insulator which eliminates copper defects (Cu flakes) during chemical-mechanical polishing (CMP). The method uses an improved hard-mask scheme with an interposed sacrificial layer between two polishing stop layers. The sacrificial layer protects the bottom stop layer from overpolishing during polish-back, which eliminates the Cu flake problem that can cause electrical intralevel shorts.
(2) Description Of The Prior Art
Advanced semiconductor processing technologies, such as high-resolution photolithography and anisotropic plasma etching, are dramatically reducing the feature sizes of semiconductor devices. This has resulted in increased device packing density on semiconductor substrates leading to Ultra Large Scale Integration (ULSI). For example, device feature sizes are now well below one-half micrometer, and the number of discrete devices utilized in making integrated circuits has increased to well over a million on many integrated circuits, such as the microprocessor, dynamic random access memory (DRAM), and the like.
It is common practice in the semiconductor industry to interconnect these discrete semiconductor devices by using multilevels of patterned metal layers to complete the integrated circuits. Interposed insulating layers having via holes between the metal layers and contact openings to the semiconducting substrate are used to electrically insulate the various metal levels.
To achieve this high density of wiring for electrical interconnections without increasing the RC time constant (resistancexc3x97capacitance), it is necessary to use metallurgies that have lower resistivity, such as copper, and to use insulating layers, such as fluorine-doped silicon glass (FSG), that has a lower dielectric constant.
Another processing problem is the accumulated effect of depositing and patterning the metal layers, one layer over another, that results in an irregular or substantially non-planar surface on an otherwise microscopically planar substrate. The rough topography becomes substantially worse as the number of metal levels increases. The downscaling of devices and the formation of the interconnecting metal wiring over the rough topography result in several processing problems. For example, improvements in photolithographic resolution requires a shallow depth of focus (DOF) during photoresist exposure, and results in unwanted distortion of the photoresist images when the photoresist is exposed over the rough topography. Another problem occurs during anisotropic etching to pattern a metal layer. It is difficult to remove the metal over steps in the rough topography because of the directional nature of the anisotropic etch. This rough topography and anisotropic etching can lead to intralevel shorts between metal lines.
One approach to circumventing these topographic problems is to use a planar technology and a damascene technique, in which trenches (also referred to as recesses) having vertical sidewalls are anisotropically plasma etched in a planar insulating layer. A metal layer, such as Cu, is deposited on the insulating layer, thereby filling the trenches in the insulating layer. The metal layer is chemically-mechanically polished (CMP) back to the insulating layer surface to form metal lines that are imbedded in, and coplanar with the insulating layer surface. In a dual damascene process contact openings and via holes are etched at the same time as the trenches, and then both the trenches and the via holes are simultaneously filled with a metal, such as Cu, and polished back at the same time to further reduce the number of processing steps.
Unfortunately, when one polishes back the copper to the low-dielectric layer, copper flakes (defects) are formed on the surface causing intralevel shorts and increasing the in-line queue time (Q-time) due to additional inspection time and wafer rework time. One method of avoiding the Cu over-polish during the damascene process is described in U.S. Pat. No. 6,071,809 to Zhao. In Zhao""s process a two-layer stack of silicon oxide and silicon nitride is used during the CMP. The silicon oxide is used as a sacrificial layer during the metal CMP to protect the silicon nitride hard mask and to prevent delamination of the underlying low-k dielectric. In U.S. Pat. No. 5,880,018 to Boech et al. a silicon dioxide layer is used in which trenches are etched and filled with a metal. The silicon dioxide is then removed and replaced with a low-k dielectric. U.S. Pat. No. 6,130,102 to White et al. is a method for making a dual inlaid electrical structure for making electrical contact to the substrate for DRAMs. After forming a planar insulating layer on the substrate, contact openings are etched in the insulating layer for the DRAM capacitor node and bit line contacts. A metal, such as iridium or ruthenium, is deposited and CMP back to form contacts. The Cu CMP issue is not addressed. U.S. Pat. No. 6,140,226 to Grill et al. is a method for making an improved dual relief pattern in a stacked hard-mask layer for a dual damascene process. The method does not address the Cu polish-back issue. In U.S. Pat. No. 6,100,184 to Zhao, a dual-damascene process is described for making electrical interconnections in a low-k dielectric insulator using a single hard-mask layer composed of silicon oxide or a metal. The method does not address the Cu CMP overpolish problem cited above.
There is still a strong need in the semiconductor industry to further improve upon the damascene or dual-damascene process to include a hard mask that eliminates the Cu flake problem while improving the polish-back uniformity across the wafer (substrate).
It is therefore a principal object of the present invention to provide an improved damascene scheme to eliminate copper-flake defects after polishing back a copper layer to form the copper metal interconnections.
Another object of this invention is to achieve this improved damascene scheme by including a second polish-stop layer (a second hard-mask layer) and a sacrificial layer over a first polish-stop layer (first hard-mask layer). The second polish-stop layer improves the planarization across the wafer during the Cu polish back while the sacrificial layer protects the underlying first hard-mask layer from damage, thereby preventing copper exposure to the fluorine in a fluorine-doped low-k dielectric layer during CMP.
The method is now briefly described for fabricating electrical interconnections on a partially completed substrate having a patterned conducting layer. This novel damascene process is an improvement over the prior art. The method utilizes an additional""second polish-stop layer to improve the Cu polish-back uniformity while a sacrificial layer between the first and second polish-stop layers prevents polish damage to the first polish-stop layer and eliminates fluorine contamination of the Cu layer that would otherwise result in copper flaking that causes electrical shorts.
The method begins by depositing a protective barrier layer on the conducting layer. A low-dielectric insulating layer, preferably fluorine-doped silicon glass, is deposited on the barrier layer to provide insulation for the highly conducting interconnecting lines. By the method of this invention, a stacked hard-mask layer is formed by depositing a first polish-stop layer, a sacrificial layer, and a second polish-stop layer on the low-dielectric insulating layer. Trenches are etched in the stacked hard-mask layer and in the low-dielectric insulating layer to provide for the electrical interconnections. Also on portions of the substrate the trenches are etched through the underlying barrier layer and into the conducting layer to provide electrical contacts between electrical interconnecting levels. Next, another barrier layer is deposited to conformally coat the trenches. A copper layer is deposited on the stacked layer sufficiently thick to fill the trenches. The copper layer is selectively polished back to the second (upper) polish-stop layer to result in a relatively uniform polish-back of the Cu layer, and the polishing is continued to partially polish into the sacrificial layer. The interposed sacrificial layer protects the first (lower) polish-stop layer from CMP damage and prevents the fluorine (F) from reacting with the copper layer that would otherwise cause Cu flakes resulting in electrical shorts. The relatively thin sacrificial layer is then removed to the first polish-stop layer using a highly selective CMP or selective plasma etch. This completes a level of the electrical interconnections. The process can be repeated for each interconnect level to complete the multilevels of wiring. The method is also applicable to a dual damascene scheme.